VHDL My timer does not work -

i have 25mhz clock in fpga , make timer returns '1' when counts 60 seconds. have 2 problems:

• i don't understand why outpout signal "count_sortie" undefined in vivado when simulate it.
• to force define signal count_sortie, add ":= 0" in testbench file simulate "count_sortie" stays equal '0' after 60 seconds delay.

here vhdl files:

    library ieee;     use ieee.std_logic_1164.all;     use ieee.std_logic_arith.all;     use ieee.std_logic_unsigned.all;       entity count         port ( clk : in  std_logic;                count_entree : in std_logic;                count_sortie : out std_logic               );     end count;      architecture behavioral of count      signal q : integer range 0 30000000 :=0;      begin          process(clk)         begin         if (clk'event , clk='1')                         while ((count_entree = '1') , (q < 25000000)) loop                   if (q < 25000000)                        q := q + 1;                       count_sortie <= '0';                    else                       count_sortie <= '1';                   end if;               end loop;         end if;         end process;      end behavioral; 

and testbench file:

library ieee; use ieee.std_logic_1164.all;  entity tbcount end tbcount;  architecture behavior of tbcount       -- component declaration unit under test (uut)      component count     port(            clk : in  std_logic;            count_entree : in std_logic;            count_sortie : out std_logic         );     end component;       --inputs     signal clk : std_logic := '0';    signal count_entree : std_logic;      --outputs     signal count_sortie : std_logic;      --clock     constant clk_period : time := 40 ns;  begin      -- instantiate unit under test (uut)    uut: count port map (           clk => clk,           count_entree => count_entree,           count_sortie => count_sortie         );     -- clock process definitions    clk_process :process    begin         clk <= '0';         wait clk_period/2;         clk <= '1';         wait clk_period/2;    end process;          -- stimulus process    stim_proc: process    begin              count_entree <= '1';        wait;    end process;  end; 

thank support.

no 1 has answered question:

• i don't understand why outpout signal "count_sortie" undefined in vivado when simulate it.
• to force define signal count_sortie, add ":= 0" in testbench file simulate "count_sortie" stays equal '0' after 60 seconds delay.

as written variable assignment := design description isn't valid vhdl.

it may worth revisiting warning messages, what's going on should apparent there. instantiated count labelled uut unbound in testbench tbcount , it's output signal not driven. far testbench concerned there not instantiation of count.

as far unasked question 'how work'

and jonathan has pointed out code can't want in event. jonathan's explanation of while loop correct, process won't work intended if uut instantiated.

the basic idea is count until q reaches 25,000,000 , set output count_sortie. note evaluating 25000000 actual add clock delay count_sortie.

if clk'event , clk = '1'     if q /= 24999999 , count_entree = '1'         q <= q + 1;     end if;     if q = 24999999         count_sortie <= '1';     else          count_sortie <= '0';     end if; end if; 

this count 24999999 , stop counting. 1 clock later count_sortie set (1).

it has property if clear or load q 0 retrigger timer there'd 1 clock delay before count_sortie went '0'.

if detrimental restore comparison 25000000 , move if statement assignment count_sortie outside bounds of if statement evaluating rising edge of clk, or make concurrent conditional signal assignment statement.

keeping assignment in process might more frugal, share same comparison count in synthesis, guaranteed.

that code in answer above this:

if clk'event , clk = '1'     if q /= 25000000 , count_entree = '1'         q <= q + 1;     end if; end if; if q = 25000000     count_sortie <= '1'; else      count_sortie <= '0'; end if; 

and q should in sensitivity list. note range of integer q needs extend it's lefmost it's rightmost assigned value.

to demonstrate i've divides count values 100,000 (for demo purposes, numeric literal 250 can set 25000000 in 3 places):

architecture behavioral of count      signal q: integer range 0 250 ;  begin  timer:      process (clk,q)     begin         if clk'event , clk = '1'             if q /= 250 , count_entree = '1'                 q <= q + 1;             end if;         end if;         if q = 250             count_sortie <= '1';         else              count_sortie <= '0';         end if;      end process;  end architecture; 

scaling q waiting clocks needlessly demonstrate count_sortie worked testbench:

(clickable)

so we've not answered question directly shown how make work correctly.

and if intending use count_sortie clock you'd want use first method (using 24999999).