vhdl - rising_edge(clk) not synthesizable -

i learning , programming vhdl lattice fpga mimic functionality of 74hct245. below code.

i keep getting statement not synthesizable since not hold value under not(clock-edge) condition. vhdl-1242 error,

 entity hct541   port (clk       : in    std_logic;                 : inout std_logic_vector(15 downto 0) := "1011101010111010";         ba        : out   std_logic_vector(15 downto 0);         n_oe, dir : in    std_logic;         m_d       : inout std_logic_vector(15 downto 0) := "0000000000000001";         d         : inout std_logic_vector(15 downto 0) := "1011101010111010";         bd        : inout std_logic_vector(15 downto 0) := "1011101010111010"); end hct541;  architecture df of hct541   signal n_oe_1, n_oe_2 : std_logic := '0'; begin    process(clk, n_oe, dir)   begin      if ((bd = "zzzzzzzzzzzzzzzz" or d = "zzzzzzzzzzzzzzzz") , n_oe = '0')       bd <= "0000000000000000";       d  <= m_d;     end if;      m_d <= m_d + '1';      clk1 : if(rising_edge(clk))        if(n_oe_1 = '0' , n_oe_2 = '0')          <= - '1';         ba <= a;       else         ba <= "zzzzzzzzzzzzzzzz";       end if;        if (n_oe = '0' , dir = '1')         d  <= m_d;         bd <= d;       elsif (n_oe = '0' , dir = '0')         bd <= bd - '1';         d  <= bd;       elsif (n_oe = '1')         bd <= "zzzzzzzzzzzzzzzz";         d  <= "zzzzzzzzzzzzzzzz";       end if;      end if clk1;    end process;  end df; 

any thoughts ?

anything wrong using rising_edge ?

a few guidelines:

1. draw picture of hardware want. code picture.
2. hardware can check 1's , 0's. checks z problematic
3. only drive tristates in combinational processes. otherwise there many surprises , mistakes.
4. many fpgas not have internal tristates, , hence, support them primary outputs.

interpreting @ jonathan drolet's comment "mixing combinational process synchronous process." think of output perspective.

your synchronous processes ideally of form:

syncproc : process (clk) begin   -- not logic here   if rising_edge(clk)    -- synch stuff.      -- logic ok in here   end if ;    -- not logic here end process syncproc ;  

your combinational processes ideally of form:

combproc : process (sig1, sig2, ...) begin   -- logic stuff here   -- not clocks here end process combproc ;  

some tools let away more.