vhdl - FPGA: No user defined clocks warning -

i working artix 7 (xc7a15tftg256) in vivado. in project shows 1 warning message.

[power 33-232] no user defined clocks found in design!

i using mrcc pin system clock input.system clock usage is

if(rising_edge(clock))     count := count+1; end if; 

kindly provide solution in problem. in advance.

this warning means there no defined clock signals in design. in cases vivado automatically constrain clocks you, if directly using input pin clock, not. using clock pin isn't enough since can use clock pins io well.

what need provide clock constraint. example is:

create_clock -period 4.000 -name myclock -waveform {0.000 2.000} [get_ports clock]. 

where period period of input clock in ns, , first number after waveform time of rising edge, , second time of falling edge. above example 250mhz, 50% duty cycle, 0 degree phase shift clock. waveform argument not necessary if have 50% duty cycle clock no phase shift.