cpu architecture - x86 segment descriptor layout - why is it weird? -


why did intel choose split base , limit of segment different parts in segment descriptor rather using contiguous bits?

see figure 5-3 of http://css.csail.mit.edu/6.858/2014/readings/i386/s05_01.htm

why did not store base address in bits 0 through 31, limit in bits 32 through 51 , use remaining position other bits (or similar layout)?

raymond chen answered question in comments:

for compatibility 80286. 80286 had maximum segment size of 2^16 , maximum base of 2^24. therefore, base , limit fields 16 , 24 bits wide. when size , base expanded 32 bits, had placed somewhere else because places taken.

here scan of segment descriptor (of code or data type) intel 80286 programmer's reference manual:

enter image description here

for comparison, here screenshot intel® 64 , ia-32 architectures software developer’s manual (volume 3a):

enter image description here

the format same, save use of reserved bits. base extended 24 32 bits, segment limit extended 16 20 bits, , additional flags added. (the "accessed" bit included part of "type" field in second screenshot)

so, in short: layout weird because backwards-compatible extension of older layout designed 16-bit processor.


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